1. Field of the Invention
This invention relates to a delay circuit for producing a certain delay time and more particularly to an improved a delay circuit for integrated circuits, such as CMOS circuits.
2. Description of the Related Art
In certain memory devices, data signals are latched at the outputs thereof after the address signals are applied, and then the memory cells are in the stand-by state to reduce the power consumption (PWL system; pulsed word line system). In such memory devices, a delay circuit is used since a waiting time of one cycle is needed.
FIGS. 4 and 5 show an example of the prior art delay circuit for use in such memory devices. FIG. 4 shows the basic construction of the conventional delay circuit wherein a capacitance 42, such as a MOS capacitor, is connected to the output side of an inverter circuit 41. FIG. 5 shows a circuit for obtaining a longer delay time. The circuit has a plurality of inverter circuits 51 through 54 with capacitors 55 through 58 provided following each of the inverter circuits. In the delay circuit having the above construction, the input/output inverting operation is performed when the threshold voltage of each inverter is exceeded so that the capacitors 55-58 are charged gradually. The similar operation takes place when the voltage value at the capacitors 55-58 exceeds the threshold voltage of the next stage inverter circuit.
FIG. 6 is a waveform diagram showing output signals of the conventional delay circuits employing one or more inverter circuits. When the inverter circuit is formed by a CMOS inverter, a waveform PA is obtained. The waveform PA starts to rise at the time .tau..sub.1 and exceeds the threshold voltage Vth of the next stage at time .tau..sub.2. At this time, .tau..sub.2 the waveform PA presents a curve that is upwardly convex due to the drive capability of the PMOS transistor in the inverter such that the voltage PA approaches the source voltage Vcc gradually.
However, the above delay circuit is subject to performance differences due to manufacturing variations. For example, when the channel length of the transistor making up the inverter circuit varies, the threshold voltage Vth is changed, with a resulting increase or decrease in the delay time. When a longer delay time is desired, the number of stages is increased correspondingly. The result is that the space required for the additional circuitry is increased in an amount corresponding to the increased number of the circuits, such as the inverter circuits. The delay time is set by the time between .tau..sub.1 and .tau..sub.2 (.tau..sub.2 -.tau..sub.1) in FIG. 6 as the reference. However, the waveform PA rises exponentially so that it is difficult to set the exact delay time. In addition, the performance differences of the circuits making up the multiple stage embodiment are added to one another to make the delay time is even less exact.